1. Field Of The Invention
The present invention relates generally to semiconductor fabrication techniques and, more particularly, to a method for fabricating small electrodes for use with a chalcogenide switching device, such as, for example, a chalcogenide memory cell.
2. Background Of The Related Art
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor. Not only does the microprocessor access a memory device to retrieve the program instructions, it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. For instance, volatile memories, such as dynamic random access memories (DRAMs), must be continually powered in order to retain their contents, but they tend to provide greater storage capability and programming options and cycles than non-volatile memories, such as read only memories (ROMs). While non-volatile memories that permit limited reprogramming exist, such as electrically erasable and programmable xe2x80x9cROMs,xe2x80x9d all true random access memories, i.e., those memories capable of 1014 programming cycles are more, are volatile memories. Although one time programmable read only memories and moderately reprogrammable memories serve many useful applications, a true nonvolatile random access memory (NVRAM) would be needed to surpass volatile memories in usefulness.
Efforts have been underway to create a commercially viable memory device, which is both random access and nonvolatile, using structure changing memory elements, as opposed to charge storage memory elements used in most commercial memory devices. The use of electrically writable and erasable phase change materials, i.e., materials which can be electrically switched between generally amorphous and generally crystalline states or between different resistive states while in crystalline form, in memory applications is known in the art and is disclosed, for example, in U.S. Pat. No. 5,296,716 to Ovshinsky et al., the disclosure of which is incorporated herein by reference. The Ovshinsky patent is believed to indicate the general state of the art and to contain a discussion of the general theory of operation of chalcogenide materials, which are a particular type of structure changing material.
As disclosed in the Ovshinsky patent, such phase change materials can be electrically switched between a first structural state, in which the material is generally amorphous, and a second structural state, in which the material has a generally crystalline local order. The material may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states. In other words, the switching of such materials is not required to take place in a binary fashion between completely amorphous and completely crystalline states. Rather, the material can be switched in incremental steps reflecting changes of local order to provide a xe2x80x9cgray scalexe2x80x9d represented by a multiplicity of conditions of local order spanning the spectrum from the completely amorphous state to the completely crystalline state.
These memory elements are monolithic, homogeneous, and formed of chalcogenide material typically selected from the group of Te, Se, Sb, Ni, and Ge. This chalcogenide material exhibits different electrical characteristics depending upon its state. For instance, in its amorphous state the material exhibits a higher resistivity than it does in its crystalline state. Such chalcogenide materials can be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods with the input of picojoules of energy. The resulting memory element is truly non-volatile. It will maintain the integrity of the information stored by the memory cell without the need for periodic refresh signals, and the data integrity of the information stored by these memory cells is not lost when power is removed from the device. The memory material is also directly overwritable so that the memory cells need not be erased, i.e., set to a specified starting point, in order to change information stored within the memory cells. Finally, the large dynamic range offered by the memory material theoretically provides for the gray scale storage of multiple bits of binary information in a single cell by mimicking the binary encoded information in analog form and, thereby, storing multiple bits of binary encoded information as a single resistance value in a single cell.
The operation of chalcogenide memory cells requires that a region of the chalcogenide memory material, called the xe2x80x9cactive region,xe2x80x9d be subjected to a current pulse to change the crystalline state of the chalcogenide material within the active region. Typically, a current density of between about 105 and 107 amperes/cm2 is needed. To obtain this current density in a commercially viable device having at least 64 million memory cells, for instance, the active region of each memory cell must be made as small as possible to minimize the total current drawn by the memory device. Currently, chalcogenide memory cells are fabricated by first creating a diode in a semiconductor substrate. A lower electrode is created over the diode, and a layer of dielectric material is deposited onto the lower electrode. A small opening is created in the dielectric layer. A second dielectric layer, typically of silicon nitride, is then deposited onto the dielectric layer and into the opening. The second dielectric layer is typically about 40 Angstroms thick. The chalcogenide material is then deposited over the second dielectric material and into the opening. An upper electrode material is then deposited over the chalcogenide material.
A conductive path is then provided from the chalcogenide material to the lower electrode material by forming a pore in the second dielectric layer by a process known as xe2x80x9cpopping.xe2x80x9d Popping involves passing an initial high current pulse through the structure to cause the second dielectric layer to breakdown. This dielectric breakdown produces a conductive path through the memory cell. Unfortunately, electrically popping the thin silicon nitride layer is not desirable for a high density memory product due to the high current and the large amount of testing time required. Furthermore, this technique may produce memory cells with differing operational characteristics, because the amount of dielectric breakdown may vary from cell to cell.
The active regions of the chalcogenide memory material within the pores of the dielectric material created by the popping technique are believed to change crystalline structure in response to applied voltage pulses of a wide range of magnitudes and pulse durations. These changes in crystalline structure alter the bulk resistance of the chalcogenide active region. Factors such as pore dimensions (e.g., diameter, thickness, and volume), chalcogenide composition, signal pulse duration, and signal pulse waveform shape may affect the magnitude of the dynamic range of resistances, the absolute endpoint resistances of the dynamic range, and the voltages required to set the memory cells at these resistances. For example, relatively thick chalcogenide films, e.g., about 4000 Angstroms, result in higher programming voltage requirements, e.g., about 15-25 volts, while relatively thin chalcogenide layers, e.g., about 500 Angstroms, result in lower programming voltage requirements, e.g., about 1-7 volts. Thus, to reduce the required programming voltage, it has been suggested that the cross-sectional area of the pore should be reduced to reduce the size of the chalcogenide element.
The energy input required to adjust the crystalline state of the chalcogenide active region of the memory cell is directly proportional to the minimum lateral dimension of the pore. In other words, programming energy decreases as the pore size decreases. Conventional chalcogenide memory cell fabrication techniques provide a minimum lateral pore dimension, e.g., the diameter or width of the pore, that is limited by the photolithographic size limit. This results in pore sizes having minimum lateral dimensions down to approximately 1 micron.
The present invention is directed to overcoming, or at least reducing the affects of, one or more of the problems set forth above.
In accordance with one aspect of the present invention, there is provided a memory cell. The memory cell includes an access device that is formed on a semiconductor substrate. A layer of dielectric material is disposed on the access device. The layer of dielectric material has a port therein. The pore is smaller that the photolithographic limit. A first layer of conductive material is disposed within the pore to form a first electrode. A layer of structure changing material is disposed on the first electrode. A second layer of conductive material is disposed on the layer of structure changing material to form a second electrode.
In accordance with another aspect of the present invention, there is provided a memory array. The memory array includes a plurality of memory cells. Each memory cell includes an access device that is formed on a semiconductor substrate. A layer of dielectric material is disposed on the access device. The layer of dielectric material has a pore therein. The pore is smaller than the photolithographic limit. A first layer of conductive material is disposed within the pore to form a first electrode. A layer of structure changing material is disposed on the first electrode. A second layer of conductive material is disposed on the layer of structure changing material to form a second electrode. The memory array also includes a grid that is coupled to the plurality of memory cells. The grid is formed by a first plurality of conductive lines that generally extend in a first direction and a second plurality of conductive lines that generally extend in a second direction.
In accordance with still another aspect of the present invention, there is provided a method of fabricating a memory cell. The method includes the steps: (a) forming an access device on a semiconductor substrate; (b) depositing a layer of dielectric material on the access device; (c) forming a pore in the layer of dielectric material, where the pore is smaller than the photolithographic limit; (d) depositing a first layer of conductive material within the pore to form a first electrode; (e) depositing a layer of structure changing material on the first electrode; and (f) depositing a second layer of conductive material on the layer of structure changing material to form a second electrode.
In accordance with yet another aspect of the present invention, there is provided a method of fabricating a memory array. The method includes the steps of (a) forming an access device on a semiconductor substrate; (b) forming a first plurality of conductive lines, where each of the first plurality of conductive lines is coupled to respective access devices; (c) depositing a layer of dielectric material on the access device; (d) forming a pore in the layer of dielectric material, where the pore is smaller than the photolithographic limit; (e) depositing a first layer of conductive material within the pore to form a first electrode; (f) depositing a layer of structure changing material on the first electrode; (g) depositing a second layer of conductive material on the layer of structure changing material to form a second electrode; and (h) forming a second plurality of conductive lines, where each of the second plurality of conductive lines is coupled to respective second electrodes.
In accordance with a further aspect of the present invention, there is provided a method of fabricating an array of pores. The method includes the steps of (a) forming a mask over a layer of dielectric material, where the mask has a plurality of windows therein exposing portions of the layer of dielectric material, and where the windows are sized at the photolithographic limit; (b) forming a spacer within each of the windows, where each spacer covers a peripheral portion of the respective exposed portion of the layer of dielectric material to create a second window that exposes a portion of the layer of dielectric material smaller than the photolithographic limit; and (c) removing the exposed portions of the layer of dielectric material created by the second windows to create the pores.
In accordance with an even further aspect of the present invention, there is provided a memory cell. The memory cell includes an access device that is formed on a semiconductor substrate. A layer of dielectric material is disposed on the access device. The layer of dielectric material has a pore therein. The pore is formed by forming a mask over the layer of dielectric material. The mask has a window therein which exposes a portion of the layer of dielectric material. The window is sized at the photolithographic limit. A spacer is formed within the window. The spacer covers a peripheral portion of the exposed portion of the layer of dielectric material to create a second window exposing a portion of the layer of dielectric material smaller than the photolithographic limit. The exposed portion of the layer of dielectric material created by the second window is removed to create the pore. A first layer of conductive material is disposed within the pore to form a first electrode. A layer of structure changing material is disposed on the first electrode. A second layer of conductive material is disposed on the layer of structure changing material to form a second electrode.